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[/] [socgen/] [trunk/] [tools/] [regtool/] [gen_registers] - Rev 135

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135 resynced with socgen, Release V1.0.0 changed tool lic to apache 2.0 jt_eaton 2754d 02h /socgen/trunk/tools/regtool/gen_registers
134 Resynced database
socgen now supports elaboration
Bad news is that it is now alot slower.
jt_eaton 3264d 04h /socgen/trunk/tools/regtool/gen_registers
131 Added elaboration databases and tools
Added bus map creation tools
jt_eaton 3339d 01h /socgen/trunk/tools/regtool/gen_registers
130 Dec 2014 major release
trimmed out some IP
replaced perl database with Berkeley
jt_eaton 3442d 19h /socgen/trunk/tools/regtool/gen_registers
128 major cleanup
added toolflows for sim,syn,documentation,linting and verilog
added documentation tools
jt_eaton 3898d 01h /socgen/trunk/tools/regtool/gen_registers
127 final cleanup before DAC jt_eaton 4012d 21h /socgen/trunk/tools/regtool/gen_registers
119 moved copyright files into /verilog
changed cde copyright to apache from gplv3
split out tools into separate subdirectories
changed design.xml files to socgen: namespace
jt_eaton 4259d 19h /socgen/trunk/tools/regtool/gen_registers

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