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[/] [socgen/] [trunk/] [tools/] [sys/] [soc_link_child] - Rev 135

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Rev	Log message	Author	Age	Path
135	resynced with socgen, Release V1.0.0 changed tool lic to apache 2.0	jt_eaton	2754d 04h	/socgen/trunk/tools/sys/soc_link_child
134	Resynced database socgen now supports elaboration Bad news is that it is now alot slower.	jt_eaton	3264d 06h	/socgen/trunk/tools/sys/soc_link_child
131	Added elaboration databases and tools Added bus map creation tools	jt_eaton	3339d 04h	/socgen/trunk/tools/sys/soc_link_child
130	Dec 2014 major release trimmed out some IP replaced perl database with Berkeley	jt_eaton	3442d 21h	/socgen/trunk/tools/sys/soc_link_child
127	final cleanup before DAC	jt_eaton	4012d 23h	/socgen/trunk/tools/sys/soc_link_child
125	Added two new 6502 cores in www.6502.org cleaned up sogen xml files and added module name control	jt_eaton	4110d 22h	/socgen/trunk/tools/sys/soc_link_child
124	beta release candidate 1 changed design.xml name aligned schema with filesystem	jt_eaton	4164d 01h	/socgen/trunk/tools/sys/soc_link_child
121	cleaned up sims, added autogenerated test bench files removed mrisc and experimental or1k code	jt_eaton	4207d 02h	/socgen/trunk/tools/sys/soc_link_child
120	clean up componentGenerators names and directories sim + lint now synthesis TestBench	jt_eaton	4225d 03h	/socgen/trunk/tools/sys/soc_link_child
119	moved copyright files into /verilog changed cde copyright to apache from gplv3 split out tools into separate subdirectories changed design.xml files to socgen: namespace	jt_eaton	4259d 21h	/socgen/trunk/tools/sys/soc_link_child
118	optimized gen_verilog added padring support added configuration support added jtag sims added accellera candidate bus defs	jt_eaton	4295d 06h	/socgen/trunk/tools/sys/soc_link_child
117	added yellow pages tools	jt_eaton	4323d 01h	/socgen/trunk/tools/sys/soc_link_child
115	split or1200_cpu up into all ip-xact components removed dead files	jt_eaton	4402d 03h	/socgen/trunk/tools/sys/soc_link_child
107	added designCfg files to all modules	jt_eaton	4447d 08h	/socgen/trunk/tools/sys/soc_link_child
101	Added new designs for minsoc release candidate convert tool set to parse proper ip-xact THIS WILL BREAK ALL THE OLD DESIGNS UNTIL I FIX THEIR IP_XACT	jt_eaton	4540d 20h	/socgen/trunk/tools/sys/soc_link_child
99	moved all projects into /projects/opencores.org added build_register added fizzim	jt_eaton	4595d 20h	/socgen/trunk/tools/sys/soc_link_child
94	socgen now supports both sim and syn views now allow each xml file to set its destination	jt_eaton	4741d 20h	/socgen/trunk/tools/sys/soc_link_child

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