URL https://opencores.org/ocsvn/storm_core/storm_core/trunk

Subversion Repositories storm_core

[/] [storm_core/] - Rev 37

Rev	Log message	Author	Age	Path
17	small synthesis-friendly update of memory components	zero_gravity	4499d 13h	/storm_core/
16	WB_TGC(5) signal fixed (indicating instruction/data fetch), coprocessor read-access bug fixed	zero_gravity	4499d 15h	/storm_core/
15	new core version! pipelined wishbone interface, I/D-cache, internal processor timer/lfsr, block transfer instructions, system mode, ... ;)	zero_gravity	4499d 20h	/storm_core/
14	- corrected stupid error in access arbiter - updated minor issues	zero_gravity	4637d 16h	/storm_core/
13	- corrected endianess converter for memory access - corrected error in temporal dependence detector	zero_gravity	4638d 12h	/storm_core/
12	- corrected error in memory write back interface - corrected immediate/register offset for byte/halfword memory access	zero_gravity	4638d 17h	/storm_core/
11		zero_gravity	4641d 21h	/storm_core/
10	New CORE version, ncluding complete system setup with inbuilt memory and wishbone interface. Ready to execute assembled ARM ASM code, arm-elf-assembler included.	zero_gravity	4641d 21h	/storm_core/
9	documentation updated	zero_gravity	4731d 19h	/storm_core/
8	documentation uploaded ;)	zero_gravity	4733d 13h	/storm_core/