URL https://opencores.org/ocsvn/t48/t48/trunk

Subversion Repositories t48

[/] [t48/] - Rev 345

Rev	Log message	Author	Age	Path
345	remove trunk after tagging rel_1_4	arniml	471d 15h	/t48/
344	release 1.4	arniml	471d 15h	/t48/
343	branch wip_t2x merged into trunk at 342	arniml	471d 16h	/t48/
342	merge branch wip_t2x into trunk	arniml	471d 16h	/t48/
341	interrupt test for 8022	arniml	494d 19h	/t48/
340	adapt int tests to ALE sampling	arniml	494d 19h	/t48/
339	fix RETI for 8022	arniml	494d 19h	/t48/
338	sample int with rising ALE	arniml	494d 19h	/t48/
337	t8022 synthesis	arniml	494d 20h	/t48/
336	docs	arniml	494d 22h	/t48/
335	simplify up41 test setup	arniml	495d 00h	/t48/
334	fix timing of sel_an*, rad	arniml	495d 12h	/t48/
333	add t8022	arniml	495d 17h	/t48/
332	mcs2x tests	arniml	496d 14h	/t48/
331	release 1.3	arniml	496d 20h	/t48/
330	add t8021	arniml	496d 20h	/t48/
329	start work on t2x	arniml	497d 13h	/t48/
328	prepare 1.3	arniml	499d 15h	/t48/
327	update integration manual	arniml	500d 13h	/t48/
326	refine status_q update	arniml	500d 17h	/t48/
325	experimental upi41_db_bus variant with asynchronous master interface	arniml	501d 00h	/t48/
324	enhance access timing in test bench	arniml	501d 00h	/t48/
323	- prevent change when master reads status - relax master access timing	arniml	501d 23h	/t48/
322	hold db_dir_o during entire access	arniml	503d 15h	/t48/
321	improve compatibility with modelsim and ghdl	arniml	504d 12h	/t48/
320	improve in test	arniml	504d 12h	/t48/
319	- add dma test - update dma logic	arniml	506d 15h	/t48/
318	t8042ah synth, fix warnings	arniml	506d 19h	/t48/
317	implement dma logic	arniml	506d 20h	/t48/
316	doc	arniml	507d 00h	/t48/