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[/] [uart16550/] [tags/] [asyst_2/] - Rev 106

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Rev Log message Author Age Path
106 New directory structure. root 5539d 03h /uart16550/tags/asyst_2/
76 This commit was manufactured by cvs2svn to create tag 'asyst_2'. 8114d 20h /tags/asyst_2/
75 Endian define added. Big Byte Endian is selected by default. mohor 8114d 20h /trunk/
74 tf_overrun signal was disabled since it was not used gorban 8119d 22h /trunk/
73 major bug in 32-bit mode that prevented register access fixed. gorban 8126d 21h /trunk/
72 UART PHY added. Files are fully operational, working on HW. mohor 8140d 04h /trunk/
71 Removed confusing comment gorban 8151d 17h /trunk/
70 tf_pop was too wide. Now it is only 1 clk cycle width. mohor 8157d 02h /trunk/
69 More than one character was stored in case of break. End of the break
was not detected correctly.		 mohor 8165d 16h /trunk/
68 lsr[7] was not showing overrun errors. mohor 8169d 00h /trunk/
67 Missing declaration of rf_push_q fixed. mohor 8176d 00h /trunk/
66 rx push changed to be only one cycle wide. mohor 8176d 00h /trunk/
65 Warnings fixed (unused signals removed). mohor 8177d 04h /trunk/
64 Warnings cleared. mohor 8177d 05h /trunk/
63 Synplicity was having troubles with the comment. mohor 8177d 05h /trunk/
62 Bug that was entered in the last update fixed (rx state machine). mohor 8178d 04h /trunk/
61 overrun signal was moved to separate block because many sequential lsr
reads were preventing data from being written to rx fifo.
underrun signal was not used and was removed from the project.		 mohor 8178d 22h /trunk/
60 Things related to msr register changed. After THRE IRQ occurs, and one
character is written to the transmit fifo, the detection of the THRE bit in the
LSR is delayed for one character time.		 mohor 8179d 03h /trunk/
59 MSR register fixed. mohor 8182d 00h /trunk/
58 After reset modem status register MSR should be reset. mohor 8182d 03h /trunk/
57 timeout irq must be set regardless of the rda irq (rda irq does not reset the
timeout counter).		 mohor 8183d 03h /trunk/
56 thre irq should be cleared only when being source of interrupt. mohor 8183d 03h /trunk/
55 some synthesis bugs fixed gorban 8183d 15h /trunk/
54 LSR status bit 0 was not cleared correctly in case of reseting the FCR (rx fifo). mohor 8184d 04h /trunk/
53 Scratch register define added. mohor 8185d 04h /trunk/
52 Scratch register added gorban 8185d 17h /trunk/
51 Igor fixed break condition bugs gorban 8185d 17h /trunk/
50 Bug in LSR[0] is fixed.
All WISHBONE signals are now sampled, so another wait-state is introduced on all transfers.		 gorban 8189d 22h /trunk/
49 committed the debug interface file gorban 8191d 16h /trunk/
48 Updated specification documentation.
Added full 32-bit data bus interface, now as default.
Address is 5-bit wide in 32-bit data bus mode.
Added wb_sel_i input to the core. It's used in the 32-bit mode.
Added debug interface with two 32-bit read-only registers in 32-bit mode.
Bits 5 and 6 of LSR are now only cleared on TX FIFO write.
My small test bench is modified to work with 32-bit mode.		 gorban 8192d 15h /trunk/

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