URL https://opencores.org/ocsvn/uart16550/uart16550/trunk

Subversion Repositories uart16550

[/] [uart16550/] [tags/] [asyst_2/] [rtl/] - Rev 106

Rev	Log message	Author	Age	Path
56	thre irq should be cleared only when being source of interrupt.	mohor	8193d 16h	/uart16550/tags/asyst_2/rtl/
55	some synthesis bugs fixed	gorban	8194d 04h	/uart16550/tags/asyst_2/rtl/
54	LSR status bit 0 was not cleared correctly in case of reseting the FCR (rx fifo).	mohor	8194d 17h	/uart16550/tags/asyst_2/rtl/
53	Scratch register define added.	mohor	8195d 17h	/uart16550/tags/asyst_2/rtl/
52	Scratch register added	gorban	8196d 06h	/uart16550/tags/asyst_2/rtl/
51	Igor fixed break condition bugs	gorban	8196d 06h	/uart16550/tags/asyst_2/rtl/
50	Bug in LSR[0] is fixed. All WISHBONE signals are now sampled, so another wait-state is introduced on all transfers.	gorban	8200d 12h	/uart16550/tags/asyst_2/rtl/
49	committed the debug interface file	gorban	8202d 05h	/uart16550/tags/asyst_2/rtl/
48	Updated specification documentation. Added full 32-bit data bus interface, now as default. Address is 5-bit wide in 32-bit data bus mode. Added wb_sel_i input to the core. It's used in the 32-bit mode. Added debug interface with two 32-bit read-only registers in 32-bit mode. Bits 5 and 6 of LSR are now only cleared on TX FIFO write. My small test bench is modified to work with 32-bit mode.	gorban	8203d 05h	/uart16550/tags/asyst_2/rtl/
47	Fixed: timeout and break didn't pay attention to current data format when counting time	gorban	8208d 07h	/uart16550/tags/asyst_2/rtl/