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[/] [uart16550/] [tags/] [asyst_3/] [rtl/] [verilog/] - Rev 106

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Rev Log message Author Age Path
106 New directory structure. root 5549d 23h /uart16550/tags/asyst_3/rtl/verilog/
77 This commit was manufactured by cvs2svn to create tag 'asyst_3'. 8125d 17h /uart16550/tags/asyst_3/rtl/verilog/
75 Endian define added. Big Byte Endian is selected by default. mohor 8125d 17h /uart16550/tags/asyst_3/rtl/verilog/
74 tf_overrun signal was disabled since it was not used gorban 8130d 18h /uart16550/tags/asyst_3/rtl/verilog/
73 major bug in 32-bit mode that prevented register access fixed. gorban 8137d 17h /uart16550/tags/asyst_3/rtl/verilog/
71 Removed confusing comment gorban 8162d 13h /uart16550/tags/asyst_3/rtl/verilog/
70 tf_pop was too wide. Now it is only 1 clk cycle width. mohor 8167d 22h /uart16550/tags/asyst_3/rtl/verilog/
69 More than one character was stored in case of break. End of the break
was not detected correctly.		 mohor 8176d 13h /uart16550/tags/asyst_3/rtl/verilog/
68 lsr[7] was not showing overrun errors. mohor 8179d 20h /uart16550/tags/asyst_3/rtl/verilog/
67 Missing declaration of rf_push_q fixed. mohor 8186d 20h /uart16550/tags/asyst_3/rtl/verilog/
66 rx push changed to be only one cycle wide. mohor 8186d 20h /uart16550/tags/asyst_3/rtl/verilog/
65 Warnings fixed (unused signals removed). mohor 8188d 01h /uart16550/tags/asyst_3/rtl/verilog/
64 Warnings cleared. mohor 8188d 02h /uart16550/tags/asyst_3/rtl/verilog/
63 Synplicity was having troubles with the comment. mohor 8188d 02h /uart16550/tags/asyst_3/rtl/verilog/
62 Bug that was entered in the last update fixed (rx state machine). mohor 8189d 01h /uart16550/tags/asyst_3/rtl/verilog/
61 overrun signal was moved to separate block because many sequential lsr
reads were preventing data from being written to rx fifo.
underrun signal was not used and was removed from the project.		 mohor 8189d 19h /uart16550/tags/asyst_3/rtl/verilog/
60 Things related to msr register changed. After THRE IRQ occurs, and one
character is written to the transmit fifo, the detection of the THRE bit in the
LSR is delayed for one character time.		 mohor 8189d 23h /uart16550/tags/asyst_3/rtl/verilog/
59 MSR register fixed. mohor 8192d 20h /uart16550/tags/asyst_3/rtl/verilog/
58 After reset modem status register MSR should be reset. mohor 8193d 00h /uart16550/tags/asyst_3/rtl/verilog/
57 timeout irq must be set regardless of the rda irq (rda irq does not reset the
timeout counter).		 mohor 8193d 23h /uart16550/tags/asyst_3/rtl/verilog/

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