URL https://opencores.org/ocsvn/uart16550/uart16550/trunk

Subversion Repositories uart16550

[/] [uart16550/] [tags/] [rel_1/] [sim/] [rtl_sim/] - Rev 106

Rev	Log message	Author	Age	Path
106	New directory structure.	root	5549d 22h	/uart16550/tags/rel_1/sim/rtl_sim/
78	This commit was manufactured by cvs2svn to create tag 'rel_1'.		8125d 15h	/uart16550/tags/rel_1/sim/rtl_sim/
50	Bug in LSR[0] is fixed. All WISHBONE signals are now sampled, so another wait-state is introduced on all transfers.	gorban	8200d 17h	/uart16550/tags/rel_1/sim/rtl_sim/
48	Updated specification documentation. Added full 32-bit data bus interface, now as default. Address is 5-bit wide in 32-bit data bus mode. Added wb_sel_i input to the core. It's used in the 32-bit mode. Added debug interface with two 32-bit read-only registers in 32-bit mode. Bits 5 and 6 of LSR are now only cleared on TX FIFO write. My small test bench is modified to work with 32-bit mode.	gorban	8203d 10h	/uart16550/tags/rel_1/sim/rtl_sim/
17	added empty directories for the required structure.	gorban	8316d 13h	/uart16550/tags/rel_1/sim/rtl_sim/
14		gorban	8316d 16h	/uart16550/tags/rel_1/sim/rtl_sim/