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[/] [uart16550/] [tags/] [rel_2/] - Rev 106

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Rev Log message Author Age Path
106 New directory structure. root 5539d 09h /uart16550/tags/rel_2/
97 This commit was manufactured by cvs2svn to create tag 'rel_2'. 7348d 15h /tags/rel_2/
96 Testbench with complete selfchecking. BUG is that THRE status is set at the end of last sent bit when TX FIFO is empty instead only when TX FIFO is empty. This sauses testcases not to finish. tadejm 7348d 15h /trunk/
95 Testbench with complete selfchecking. BUG is that THRE status is set at the end of last sent bit when TX FIFO is empty instead only when TX FIFO is empty. This causes testcases not to finish. tadejm 7348d 15h /trunk/
94 Testbench with complete selfchecking. BUG is that THRE status is set at the end of last sent bit when TX FIFO is empty instead when only TX FIFO gets empty. This causes testcases not to finish. tadejm 7348d 15h /trunk/
93 Testbench with complete selfchecking. BUG is that THRE status is set at the end of last sent bit when TX FIFO is empty instead when only TX FIFO gets empty. This causes testcases not to finish. tadejm 7348d 15h /trunk/
92 This is revision 1.4, revision 1.5 was put there by mistake. simons 7462d 08h /trunk/
91 Removed files due to new complete testbench. tadejm 7462d 23h /trunk/
90 Add Flextronics header avisha 7465d 06h /trunk/
89 adjusted comment + define dries 7545d 12h /trunk/
88 added clearing the receiver fifo statuses on resets gorban 7608d 01h /trunk/
87 This fixes errors in some cases when data is being read and put to the FIFO at the same time. Patch is submitted by Scott Furman. Update is very recommended. gorban 7638d 02h /trunk/
86 restored include for uart_defines.v in uart_test.v gorban 7908d 06h /trunk/
85 Updated documentation to include latest changes. gorban 7941d 22h /trunk/
84 The uart_defines.v file is included again in sources. gorban 7954d 22h /trunk/
83 Reverted to include uart_defines.v file in other files again. gorban 7954d 22h /trunk/
82 Updated to work with latest core. gorban 7961d 20h /trunk/
81 Added lastest additions. gorban 7961d 20h /trunk/
80 Remove uart_fifo.v because it is replaced by other 2 files. gorban 7961d 20h /trunk/
79 Bug Fixes:
* Possible loss of sync and bad reception of stop bit on slow baud rates fixed.
Problem reported by Kenny.Tung.
* Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers.

Improvements:
* Made FIFO's as general inferrable memory where possible.
So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx).
This saves about 1/3 of the Slice count and reduces P&R and synthesis times.

* Added optional baudrate output (baud_o).
This is identical to BAUDOUT* signal on 16550 chip.
It outputs 16xbit_clock_rate - the divided clock.
It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use.		 gorban 7961d 20h /trunk/

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