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[/] [uart16550/] [tags/] [rel_2/] [rtl/] [verilog/] - Rev 106

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Rev Log message Author Age Path
106 New directory structure. root 5562d 09h /uart16550/tags/rel_2/rtl/verilog/
97 This commit was manufactured by cvs2svn to create tag 'rel_2'. 7371d 15h /uart16550/tags/rel_2/rtl/verilog/
89 adjusted comment + define dries 7568d 11h /uart16550/tags/rel_2/rtl/verilog/
88 added clearing the receiver fifo statuses on resets gorban 7631d 01h /uart16550/tags/rel_2/rtl/verilog/
87 This fixes errors in some cases when data is being read and put to the FIFO at the same time. Patch is submitted by Scott Furman. Update is very recommended. gorban 7661d 02h /uart16550/tags/rel_2/rtl/verilog/
84 The uart_defines.v file is included again in sources. gorban 7977d 22h /uart16550/tags/rel_2/rtl/verilog/
80 Remove uart_fifo.v because it is replaced by other 2 files. gorban 7984d 20h /uart16550/tags/rel_2/rtl/verilog/
79 Bug Fixes:
* Possible loss of sync and bad reception of stop bit on slow baud rates fixed.
Problem reported by Kenny.Tung.
* Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers.

Improvements:
* Made FIFO's as general inferrable memory where possible.
So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx).
This saves about 1/3 of the Slice count and reduces P&R and synthesis times.

* Added optional baudrate output (baud_o).
This is identical to BAUDOUT* signal on 16550 chip.
It outputs 16xbit_clock_rate - the divided clock.
It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use.		 gorban 7984d 20h /uart16550/tags/rel_2/rtl/verilog/
75 Endian define added. Big Byte Endian is selected by default. mohor 8138d 02h /uart16550/tags/rel_2/rtl/verilog/
74 tf_overrun signal was disabled since it was not used gorban 8143d 03h /uart16550/tags/rel_2/rtl/verilog/
73 major bug in 32-bit mode that prevented register access fixed. gorban 8150d 03h /uart16550/tags/rel_2/rtl/verilog/
71 Removed confusing comment gorban 8174d 23h /uart16550/tags/rel_2/rtl/verilog/
70 tf_pop was too wide. Now it is only 1 clk cycle width. mohor 8180d 07h /uart16550/tags/rel_2/rtl/verilog/
69 More than one character was stored in case of break. End of the break
was not detected correctly.		 mohor 8188d 22h /uart16550/tags/rel_2/rtl/verilog/
68 lsr[7] was not showing overrun errors. mohor 8192d 05h /uart16550/tags/rel_2/rtl/verilog/
67 Missing declaration of rf_push_q fixed. mohor 8199d 05h /uart16550/tags/rel_2/rtl/verilog/
66 rx push changed to be only one cycle wide. mohor 8199d 05h /uart16550/tags/rel_2/rtl/verilog/
65 Warnings fixed (unused signals removed). mohor 8200d 10h /uart16550/tags/rel_2/rtl/verilog/
64 Warnings cleared. mohor 8200d 11h /uart16550/tags/rel_2/rtl/verilog/
63 Synplicity was having troubles with the comment. mohor 8200d 11h /uart16550/tags/rel_2/rtl/verilog/

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