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[/] [uart16550/] [tags/] [rel_3/] [bench/] - Rev 106

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Rev Log message Author Age Path
106 New directory structure. root 5539d 07h /uart16550/tags/rel_3/bench/
102 This commit was manufactured by cvs2svn to create tag 'rel_3'. 7293d 05h /uart16550/tags/rel_3/bench/
94 Testbench with complete selfchecking. BUG is that THRE status is set at the end of last sent bit when TX FIFO is empty instead when only TX FIFO gets empty. This causes testcases not to finish. tadejm 7348d 13h /uart16550/tags/rel_3/bench/
93 Testbench with complete selfchecking. BUG is that THRE status is set at the end of last sent bit when TX FIFO is empty instead when only TX FIFO gets empty. This causes testcases not to finish. tadejm 7348d 14h /uart16550/tags/rel_3/bench/
91 Removed files due to new complete testbench. tadejm 7462d 22h /uart16550/tags/rel_3/bench/
86 restored include for uart_defines.v in uart_test.v gorban 7908d 05h /uart16550/tags/rel_3/bench/
83 Reverted to include uart_defines.v file in other files again. gorban 7954d 20h /uart16550/tags/rel_3/bench/
72 UART PHY added. Files are fully operational, working on HW. mohor 8140d 09h /uart16550/tags/rel_3/bench/
48 Updated specification documentation.
Added full 32-bit data bus interface, now as default.
Address is 5-bit wide in 32-bit data bus mode.
Added wb_sel_i input to the core. It's used in the 32-bit mode.
Added debug interface with two 32-bit read-only registers in 32-bit mode.
Bits 5 and 6 of LSR are now only cleared on TX FIFO write.
My small test bench is modified to work with 32-bit mode.		 gorban 8192d 20h /uart16550/tags/rel_3/bench/
38 small update to test interrupts gorban 8219d 00h /uart16550/tags/rel_3/bench/
17 added empty directories for the required structure. gorban 8305d 23h /uart16550/tags/rel_3/bench/
14 gorban 8306d 01h /uart16550/tags/rel_3/bench/

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