OpenCores
URL https://opencores.org/ocsvn/uart16550/uart16550/trunk

Subversion Repositories uart16550

[/] [uart16550/] [tags/] [rel_3/] [doc/] - Rev 106

Rev

Filtering Options

Clear current filter

Rev Log message Author Age Path
106 New directory structure. root 5539d 08h /uart16550/tags/rel_3/doc/
102 This commit was manufactured by cvs2svn to create tag 'rel_3'. 7293d 05h /uart16550/tags/rel_3/doc/
92 This is revision 1.4, revision 1.5 was put there by mistake. simons 7462d 07h /uart16550/tags/rel_3/doc/
90 Add Flextronics header avisha 7465d 05h /uart16550/tags/rel_3/doc/
85 Updated documentation to include latest changes. gorban 7941d 21h /uart16550/tags/rel_3/doc/
83 Reverted to include uart_defines.v file in other files again. gorban 7954d 21h /uart16550/tags/rel_3/doc/
81 Added lastest additions. gorban 7961d 19h /uart16550/tags/rel_3/doc/
48 Updated specification documentation.
Added full 32-bit data bus interface, now as default.
Address is 5-bit wide in 32-bit data bus mode.
Added wb_sel_i input to the core. It's used in the 32-bit mode.
Added debug interface with two 32-bit read-only registers in 32-bit mode.
Bits 5 and 6 of LSR are now only cleared on TX FIFO write.
My small test bench is modified to work with 32-bit mode.
gorban 8192d 20h /uart16550/tags/rel_3/doc/
20 typo bug fixes gorban 8297d 22h /uart16550/tags/rel_3/doc/
14 gorban 8306d 01h /uart16550/tags/rel_3/doc/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.