URL https://opencores.org/ocsvn/uart16550/uart16550/trunk

Subversion Repositories uart16550

[/] [uart16550/] [tags/] [rel_4/] - Rev 106

Rev	Log message	Author	Age	Path
83	Reverted to include uart_defines.v file in other files again.	gorban	7954d 17h	/uart16550/tags/rel_4/
82	Updated to work with latest core.	gorban	7961d 15h	/uart16550/tags/rel_4/
81	Added lastest additions.	gorban	7961d 15h	/uart16550/tags/rel_4/
80	Remove uart_fifo.v because it is replaced by other 2 files.	gorban	7961d 15h	/uart16550/tags/rel_4/
79	Bug Fixes: * Possible loss of sync and bad reception of stop bit on slow baud rates fixed. Problem reported by Kenny.Tung. * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers. Improvements: * Made FIFO's as general inferrable memory where possible. So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx). This saves about 1/3 of the Slice count and reduces P&R and synthesis times. * Added optional baudrate output (baud_o). This is identical to BAUDOUT* signal on 16550 chip. It outputs 16xbit_clock_rate - the divided clock. It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use.	gorban	7961d 15h	/uart16550/tags/rel_4/
75	Endian define added. Big Byte Endian is selected by default.	mohor	8114d 21h	/uart16550/tags/rel_4/
74	tf_overrun signal was disabled since it was not used	gorban	8119d 23h	/uart16550/tags/rel_4/
73	major bug in 32-bit mode that prevented register access fixed.	gorban	8126d 22h	/uart16550/tags/rel_4/
72	UART PHY added. Files are fully operational, working on HW.	mohor	8140d 06h	/uart16550/tags/rel_4/
71	Removed confusing comment	gorban	8151d 18h	/uart16550/tags/rel_4/