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[/] [uart16550/] [tags/] [rel_4/] [rtl/] - Rev 106

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Rev Log message Author Age Path
106 New directory structure. root 5561d 03h /uart16550/tags/rel_4/rtl/
104 This commit was manufactured by cvs2svn to create tag 'rel_4'. 7286d 23h /uart16550/tags/rel_4/rtl/
103 Brandl Tobias repaired a bug regarding frame error in receiver when brake is received. tadejm 7286d 23h /uart16550/tags/rel_4/rtl/
101 Added 2 LSB address generation dependent on select lines and LITLE/BIG endian when UART is in 32-bit mode. tadejm 7315d 01h /uart16550/tags/rel_4/rtl/
100 Repaired bug in receiver. When stop bit is sampled and next clock RX input was '0', state machine stayed locked until next '1' which cause loosing at least start bit in case of larger difference of bit times between 2 UARTs. tadejm 7315d 02h /uart16550/tags/rel_4/rtl/
99 Added synchronizer flops for RX input. tadejm 7315d 02h /uart16550/tags/rel_4/rtl/
98 Added to synchronize RX input to Wishbone clock. tadejm 7315d 02h /uart16550/tags/rel_4/rtl/
89 adjusted comment + define dries 7567d 06h /uart16550/tags/rel_4/rtl/
88 added clearing the receiver fifo statuses on resets gorban 7629d 19h /uart16550/tags/rel_4/rtl/
87 This fixes errors in some cases when data is being read and put to the FIFO at the same time. Patch is submitted by Scott Furman. Update is very recommended. gorban 7659d 21h /uart16550/tags/rel_4/rtl/
84 The uart_defines.v file is included again in sources. gorban 7976d 16h /uart16550/tags/rel_4/rtl/
80 Remove uart_fifo.v because it is replaced by other 2 files. gorban 7983d 14h /uart16550/tags/rel_4/rtl/
79 Bug Fixes:
* Possible loss of sync and bad reception of stop bit on slow baud rates fixed.
Problem reported by Kenny.Tung.
* Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers.

Improvements:
* Made FIFO's as general inferrable memory where possible.
So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx).
This saves about 1/3 of the Slice count and reduces P&R and synthesis times.

* Added optional baudrate output (baud_o).
This is identical to BAUDOUT* signal on 16550 chip.
It outputs 16xbit_clock_rate - the divided clock.
It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use.		 gorban 7983d 14h /uart16550/tags/rel_4/rtl/
75 Endian define added. Big Byte Endian is selected by default. mohor 8136d 20h /uart16550/tags/rel_4/rtl/
74 tf_overrun signal was disabled since it was not used gorban 8141d 22h /uart16550/tags/rel_4/rtl/
73 major bug in 32-bit mode that prevented register access fixed. gorban 8148d 21h /uart16550/tags/rel_4/rtl/
71 Removed confusing comment gorban 8173d 17h /uart16550/tags/rel_4/rtl/
70 tf_pop was too wide. Now it is only 1 clk cycle width. mohor 8179d 02h /uart16550/tags/rel_4/rtl/
69 More than one character was stored in case of break. End of the break
was not detected correctly.		 mohor 8187d 17h /uart16550/tags/rel_4/rtl/
68 lsr[7] was not showing overrun errors. mohor 8191d 00h /uart16550/tags/rel_4/rtl/

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