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[/] [uart16550/] [tags/] [rel_4/] [sim/] - Rev 106

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Rev Log message Author Age Path
106 New directory structure. root 5538d 14h /uart16550/tags/rel_4/sim/
104 This commit was manufactured by cvs2svn to create tag 'rel_4'. 7264d 09h /uart16550/tags/rel_4/sim/
96 Testbench with complete selfchecking. BUG is that THRE status is set at the end of last sent bit when TX FIFO is empty instead only when TX FIFO is empty. This sauses testcases not to finish. tadejm 7347d 20h /uart16550/tags/rel_4/sim/
95 Testbench with complete selfchecking. BUG is that THRE status is set at the end of last sent bit when TX FIFO is empty instead only when TX FIFO is empty. This causes testcases not to finish. tadejm 7347d 20h /uart16550/tags/rel_4/sim/
83 Reverted to include uart_defines.v file in other files again. gorban 7954d 03h /uart16550/tags/rel_4/sim/
82 Updated to work with latest core. gorban 7961d 01h /uart16550/tags/rel_4/sim/
50 Bug in LSR[0] is fixed.
All WISHBONE signals are now sampled, so another wait-state is introduced on all transfers.		 gorban 8189d 09h /uart16550/tags/rel_4/sim/
48 Updated specification documentation.
Added full 32-bit data bus interface, now as default.
Address is 5-bit wide in 32-bit data bus mode.
Added wb_sel_i input to the core. It's used in the 32-bit mode.
Added debug interface with two 32-bit read-only registers in 32-bit mode.
Bits 5 and 6 of LSR are now only cleared on TX FIFO write.
My small test bench is modified to work with 32-bit mode.		 gorban 8192d 02h /uart16550/tags/rel_4/sim/
17 added empty directories for the required structure. gorban 8305d 05h /uart16550/tags/rel_4/sim/
14 gorban 8305d 08h /uart16550/tags/rel_4/sim/

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