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[/] [uart16550/] [trunk/] [bench/] [verilog/] - Rev 106

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Rev	Log message	Author	Age	Path
106	New directory structure.	root	5548d 12h	/uart16550/trunk/bench/verilog/
94	Testbench with complete selfchecking. BUG is that THRE status is set at the end of last sent bit when TX FIFO is empty instead when only TX FIFO gets empty. This causes testcases not to finish.	tadejm	7357d 18h	/uart16550/trunk/bench/verilog/
93	Testbench with complete selfchecking. BUG is that THRE status is set at the end of last sent bit when TX FIFO is empty instead when only TX FIFO gets empty. This causes testcases not to finish.	tadejm	7357d 18h	/uart16550/trunk/bench/verilog/
91	Removed files due to new complete testbench.	tadejm	7472d 02h	/uart16550/trunk/bench/verilog/
86	restored include for uart_defines.v in uart_test.v	gorban	7917d 10h	/uart16550/trunk/bench/verilog/
83	Reverted to include uart_defines.v file in other files again.	gorban	7964d 01h	/uart16550/trunk/bench/verilog/
72	UART PHY added. Files are fully operational, working on HW.	mohor	8149d 13h	/uart16550/trunk/bench/verilog/
48	Updated specification documentation. Added full 32-bit data bus interface, now as default. Address is 5-bit wide in 32-bit data bus mode. Added wb_sel_i input to the core. It's used in the 32-bit mode. Added debug interface with two 32-bit read-only registers in 32-bit mode. Bits 5 and 6 of LSR are now only cleared on TX FIFO write. My small test bench is modified to work with 32-bit mode.	gorban	8202d 01h	/uart16550/trunk/bench/verilog/
38	small update to test interrupts	gorban	8228d 04h	/uart16550/trunk/bench/verilog/
14		gorban	8315d 06h	/uart16550/trunk/bench/verilog/

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