URL https://opencores.org/ocsvn/uart16550/uart16550/trunk

Subversion Repositories uart16550

[/] [uart16550/] [trunk/] [doc/] [src/] - Rev 106

Rev	Log message	Author	Age	Path
106	New directory structure.	root	5548d 12h	/uart16550/trunk/doc/src/
92	This is revision 1.4, revision 1.5 was put there by mistake.	simons	7471d 11h	/uart16550/trunk/doc/src/
90	Add Flextronics header	avisha	7474d 09h	/uart16550/trunk/doc/src/
85	Updated documentation to include latest changes.	gorban	7951d 02h	/uart16550/trunk/doc/src/
48	Updated specification documentation. Added full 32-bit data bus interface, now as default. Address is 5-bit wide in 32-bit data bus mode. Added wb_sel_i input to the core. It's used in the 32-bit mode. Added debug interface with two 32-bit read-only registers in 32-bit mode. Bits 5 and 6 of LSR are now only cleared on TX FIFO write. My small test bench is modified to work with 32-bit mode.	gorban	8202d 01h	/uart16550/trunk/doc/src/
20	typo bug fixes	gorban	8307d 03h	/uart16550/trunk/doc/src/
14		gorban	8315d 06h	/uart16550/trunk/doc/src/