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[/] [uart16550/] [trunk/] [rtl/] [verilog/] - Rev 106

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Rev Log message Author Age Path
106 New directory structure. root 5535d 04h /uart16550/trunk/rtl/verilog/
105 Timeout interrupt should be generated only when there is at least ony
character in the fifo.		 igorm 7104d 05h /uart16550/trunk/rtl/verilog/
103 Brandl Tobias repaired a bug regarding frame error in receiver when brake is received. tadejm 7260d 23h /uart16550/trunk/rtl/verilog/
101 Added 2 LSB address generation dependent on select lines and LITLE/BIG endian when UART is in 32-bit mode. tadejm 7289d 02h /uart16550/trunk/rtl/verilog/
100 Repaired bug in receiver. When stop bit is sampled and next clock RX input was '0', state machine stayed locked until next '1' which cause loosing at least start bit in case of larger difference of bit times between 2 UARTs. tadejm 7289d 02h /uart16550/trunk/rtl/verilog/
99 Added synchronizer flops for RX input. tadejm 7289d 02h /uart16550/trunk/rtl/verilog/
98 Added to synchronize RX input to Wishbone clock. tadejm 7289d 02h /uart16550/trunk/rtl/verilog/
89 adjusted comment + define dries 7541d 07h /uart16550/trunk/rtl/verilog/
88 added clearing the receiver fifo statuses on resets gorban 7603d 20h /uart16550/trunk/rtl/verilog/
87 This fixes errors in some cases when data is being read and put to the FIFO at the same time. Patch is submitted by Scott Furman. Update is very recommended. gorban 7633d 22h /uart16550/trunk/rtl/verilog/
84 The uart_defines.v file is included again in sources. gorban 7950d 17h /uart16550/trunk/rtl/verilog/
80 Remove uart_fifo.v because it is replaced by other 2 files. gorban 7957d 15h /uart16550/trunk/rtl/verilog/
79 Bug Fixes:
* Possible loss of sync and bad reception of stop bit on slow baud rates fixed.
Problem reported by Kenny.Tung.
* Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers.

Improvements:
* Made FIFO's as general inferrable memory where possible.
So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx).
This saves about 1/3 of the Slice count and reduces P&R and synthesis times.

* Added optional baudrate output (baud_o).
This is identical to BAUDOUT* signal on 16550 chip.
It outputs 16xbit_clock_rate - the divided clock.
It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use.		 gorban 7957d 15h /uart16550/trunk/rtl/verilog/
75 Endian define added. Big Byte Endian is selected by default. mohor 8110d 21h /uart16550/trunk/rtl/verilog/
74 tf_overrun signal was disabled since it was not used gorban 8115d 23h /uart16550/trunk/rtl/verilog/
73 major bug in 32-bit mode that prevented register access fixed. gorban 8122d 22h /uart16550/trunk/rtl/verilog/
71 Removed confusing comment gorban 8147d 18h /uart16550/trunk/rtl/verilog/
70 tf_pop was too wide. Now it is only 1 clk cycle width. mohor 8153d 03h /uart16550/trunk/rtl/verilog/
69 More than one character was stored in case of break. End of the break
was not detected correctly.		 mohor 8161d 18h /uart16550/trunk/rtl/verilog/
68 lsr[7] was not showing overrun errors. mohor 8165d 01h /uart16550/trunk/rtl/verilog/

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