URL https://opencores.org/ocsvn/uart16550/uart16550/trunk

Subversion Repositories uart16550

[/] [uart16550/] [trunk/] [rtl/] [verilog/] - Rev 106

Rev	Log message	Author	Age	Path
67	Missing declaration of rf_push_q fixed.	mohor	8185d 05h	/uart16550/trunk/rtl/verilog/
66	rx push changed to be only one cycle wide.	mohor	8185d 05h	/uart16550/trunk/rtl/verilog/
65	Warnings fixed (unused signals removed).	mohor	8186d 10h	/uart16550/trunk/rtl/verilog/
64	Warnings cleared.	mohor	8186d 10h	/uart16550/trunk/rtl/verilog/
63	Synplicity was having troubles with the comment.	mohor	8186d 11h	/uart16550/trunk/rtl/verilog/
62	Bug that was entered in the last update fixed (rx state machine).	mohor	8187d 09h	/uart16550/trunk/rtl/verilog/
61	overrun signal was moved to separate block because many sequential lsr reads were preventing data from being written to rx fifo. underrun signal was not used and was removed from the project.	mohor	8188d 04h	/uart16550/trunk/rtl/verilog/
60	Things related to msr register changed. After THRE IRQ occurs, and one character is written to the transmit fifo, the detection of the THRE bit in the LSR is delayed for one character time.	mohor	8188d 08h	/uart16550/trunk/rtl/verilog/
59	MSR register fixed.	mohor	8191d 05h	/uart16550/trunk/rtl/verilog/
58	After reset modem status register MSR should be reset.	mohor	8191d 08h	/uart16550/trunk/rtl/verilog/