URL https://opencores.org/ocsvn/uart16550/uart16550/trunk

Subversion Repositories uart16550

[/] [uart16550/] [trunk/] [rtl/] [verilog/] [uart_debug_if.v] - Rev 106

Rev	Log message	Author	Age	Path
106	New directory structure.	root	5534d 22h	/uart16550/trunk/rtl/verilog/uart_debug_if.v
84	The uart_defines.v file is included again in sources.	gorban	7950d 11h	/uart16550/trunk/rtl/verilog/uart_debug_if.v
79	Bug Fixes: * Possible loss of sync and bad reception of stop bit on slow baud rates fixed. Problem reported by Kenny.Tung. * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers. Improvements: * Made FIFO's as general inferrable memory where possible. So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx). This saves about 1/3 of the Slice count and reduces P&R and synthesis times. * Added optional baudrate output (baud_o). This is identical to BAUDOUT* signal on 16550 chip. It outputs 16xbit_clock_rate - the divided clock. It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use.	gorban	7957d 10h	/uart16550/trunk/rtl/verilog/uart_debug_if.v
65	Warnings fixed (unused signals removed).	mohor	8173d 00h	/uart16550/trunk/rtl/verilog/uart_debug_if.v
55	some synthesis bugs fixed	gorban	8179d 10h	/uart16550/trunk/rtl/verilog/uart_debug_if.v
49	committed the debug interface file	gorban	8187d 11h	/uart16550/trunk/rtl/verilog/uart_debug_if.v