URL https://opencores.org/ocsvn/uart16550/uart16550/trunk

Subversion Repositories uart16550

[/] [uart16550/] [trunk/] [rtl/] [verilog/] [uart_sync_flops.v] - Rev 106

Rev	Log message	Author	Age	Path
106	New directory structure.	root	5535d 07h	/uart16550/trunk/rtl/verilog/uart_sync_flops.v
98	Added to synchronize RX input to Wishbone clock.	tadejm	7289d 05h	/uart16550/trunk/rtl/verilog/uart_sync_flops.v