OpenCores
URL https://opencores.org/ocsvn/uart16550/uart16550/trunk

Subversion Repositories uart16550

[/] [uart16550/] [trunk/] [rtl/] [verilog/] [uart_wb.v] - Rev 106

Rev

Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
106 New directory structure. root 5535d 03h /uart16550/trunk/rtl/verilog/uart_wb.v
101 Added 2 LSB address generation dependent on select lines and LITLE/BIG endian when UART is in 32-bit mode. tadejm 7289d 01h /uart16550/trunk/rtl/verilog/uart_wb.v
84 The uart_defines.v file is included again in sources. gorban 7950d 16h /uart16550/trunk/rtl/verilog/uart_wb.v
79 Bug Fixes:
* Possible loss of sync and bad reception of stop bit on slow baud rates fixed.
Problem reported by Kenny.Tung.
* Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers.

Improvements:
* Made FIFO's as general inferrable memory where possible.
So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx).
This saves about 1/3 of the Slice count and reduces P&R and synthesis times.

* Added optional baudrate output (baud_o).
This is identical to BAUDOUT* signal on 16550 chip.
It outputs 16xbit_clock_rate - the divided clock.
It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use.		 gorban 7957d 15h /uart16550/trunk/rtl/verilog/uart_wb.v
75 Endian define added. Big Byte Endian is selected by default. mohor 8110d 21h /uart16550/trunk/rtl/verilog/uart_wb.v
73 major bug in 32-bit mode that prevented register access fixed. gorban 8122d 21h /uart16550/trunk/rtl/verilog/uart_wb.v
64 Warnings cleared. mohor 8173d 06h /uart16550/trunk/rtl/verilog/uart_wb.v
50 Bug in LSR[0] is fixed.
All WISHBONE signals are now sampled, so another wait-state is introduced on all transfers.		 gorban 8185d 23h /uart16550/trunk/rtl/verilog/uart_wb.v
48 Updated specification documentation.
Added full 32-bit data bus interface, now as default.
Address is 5-bit wide in 32-bit data bus mode.
Added wb_sel_i input to the core. It's used in the 32-bit mode.
Added debug interface with two 32-bit read-only registers in 32-bit mode.
Bits 5 and 6 of LSR are now only cleared on TX FIFO write.
My small test bench is modified to work with 32-bit mode.		 gorban 8188d 16h /uart16550/trunk/rtl/verilog/uart_wb.v
33 Small synopsis fixes gorban 8233d 04h /uart16550/trunk/rtl/verilog/uart_wb.v
29 Things connected to parity changed.
Clock devider changed.		 mohor 8289d 17h /uart16550/trunk/rtl/verilog/uart_wb.v
27 Stop bit bug fixed.
Parity bug fixed.
WISHBONE read cycle bug fixed,
OE indicator (Overrun Error) bug fixed.
PE indicator (Parity Error) bug fixed.
Register read bug fixed.		 mohor 8290d 21h /uart16550/trunk/rtl/verilog/uart_wb.v

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.