URL https://opencores.org/ocsvn/uart16550/uart16550/trunk

Subversion Repositories uart16550

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Rev	Log message	Author	Age	Path
108	Added old uploaded documents to new repository.	root	5530d 08h	/
107	Added old uploaded documents to new repository.	root	5530d 14h	/
106	New directory structure.	root	5530d 14h	/
105	Timeout interrupt should be generated only when there is at least ony character in the fifo.	igorm	7099d 15h	/
104	This commit was manufactured by cvs2svn to create tag 'rel_4'.		7256d 09h	/
103	Brandl Tobias repaired a bug regarding frame error in receiver when brake is received.	tadejm	7256d 09h	/
102	This commit was manufactured by cvs2svn to create tag 'rel_3'.		7284d 11h	/
101	Added 2 LSB address generation dependent on select lines and LITLE/BIG endian when UART is in 32-bit mode.	tadejm	7284d 11h	/
100	Repaired bug in receiver. When stop bit is sampled and next clock RX input was '0', state machine stayed locked until next '1' which cause loosing at least start bit in case of larger difference of bit times between 2 UARTs.	tadejm	7284d 12h	/
99	Added synchronizer flops for RX input.	tadejm	7284d 12h	/
98	Added to synchronize RX input to Wishbone clock.	tadejm	7284d 12h	/
97	This commit was manufactured by cvs2svn to create tag 'rel_2'.		7339d 20h	/
96	Testbench with complete selfchecking. BUG is that THRE status is set at the end of last sent bit when TX FIFO is empty instead only when TX FIFO is empty. This sauses testcases not to finish.	tadejm	7339d 20h	/
95	Testbench with complete selfchecking. BUG is that THRE status is set at the end of last sent bit when TX FIFO is empty instead only when TX FIFO is empty. This causes testcases not to finish.	tadejm	7339d 20h	/
94	Testbench with complete selfchecking. BUG is that THRE status is set at the end of last sent bit when TX FIFO is empty instead when only TX FIFO gets empty. This causes testcases not to finish.	tadejm	7339d 20h	/
93	Testbench with complete selfchecking. BUG is that THRE status is set at the end of last sent bit when TX FIFO is empty instead when only TX FIFO gets empty. This causes testcases not to finish.	tadejm	7339d 20h	/
92	This is revision 1.4, revision 1.5 was put there by mistake.	simons	7453d 13h	/
91	Removed files due to new complete testbench.	tadejm	7454d 04h	/
90	Add Flextronics header	avisha	7456d 11h	/
89	adjusted comment + define	dries	7536d 16h	/

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Subversion Repositories uart16550

[/] - Rev 108

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