URL https://opencores.org/ocsvn/uart16550/uart16550/trunk

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Rev	Log message	Author	Age	Path
76	This commit was manufactured by cvs2svn to create tag 'asyst_2'.		8114d 14h	/
75	Endian define added. Big Byte Endian is selected by default.	mohor	8114d 14h	/
74	tf_overrun signal was disabled since it was not used	gorban	8119d 15h	/
73	major bug in 32-bit mode that prevented register access fixed.	gorban	8126d 14h	/
72	UART PHY added. Files are fully operational, working on HW.	mohor	8139d 22h	/
71	Removed confusing comment	gorban	8151d 10h	/
70	tf_pop was too wide. Now it is only 1 clk cycle width.	mohor	8156d 19h	/
69	More than one character was stored in case of break. End of the break was not detected correctly.	mohor	8165d 10h	/
68	lsr[7] was not showing overrun errors.	mohor	8168d 17h	/
67	Missing declaration of rf_push_q fixed.	mohor	8175d 17h	/
66	rx push changed to be only one cycle wide.	mohor	8175d 17h	/
65	Warnings fixed (unused signals removed).	mohor	8176d 22h	/
64	Warnings cleared.	mohor	8176d 22h	/
63	Synplicity was having troubles with the comment.	mohor	8176d 23h	/
62	Bug that was entered in the last update fixed (rx state machine).	mohor	8177d 21h	/
61	overrun signal was moved to separate block because many sequential lsr reads were preventing data from being written to rx fifo. underrun signal was not used and was removed from the project.	mohor	8178d 16h	/
60	Things related to msr register changed. After THRE IRQ occurs, and one character is written to the transmit fifo, the detection of the THRE bit in the LSR is delayed for one character time.	mohor	8178d 20h	/
59	MSR register fixed.	mohor	8181d 17h	/
58	After reset modem status register MSR should be reset.	mohor	8181d 20h	/
57	timeout irq must be set regardless of the rda irq (rda irq does not reset the timeout counter).	mohor	8182d 20h	/

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