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Rev	Log message	Author	Age	Path
76	This commit was manufactured by cvs2svn to create tag 'asyst_2'.		8125d 12h	/
75	Endian define added. Big Byte Endian is selected by default.	mohor	8125d 12h	/
74	tf_overrun signal was disabled since it was not used	gorban	8130d 13h	/
73	major bug in 32-bit mode that prevented register access fixed.	gorban	8137d 13h	/
72	UART PHY added. Files are fully operational, working on HW.	mohor	8150d 20h	/
71	Removed confusing comment	gorban	8162d 09h	/
70	tf_pop was too wide. Now it is only 1 clk cycle width.	mohor	8167d 17h	/
69	More than one character was stored in case of break. End of the break was not detected correctly.	mohor	8176d 08h	/
68	lsr[7] was not showing overrun errors.	mohor	8179d 16h	/
67	Missing declaration of rf_push_q fixed.	mohor	8186d 15h	/
66	rx push changed to be only one cycle wide.	mohor	8186d 16h	/
65	Warnings fixed (unused signals removed).	mohor	8187d 20h	/
64	Warnings cleared.	mohor	8187d 21h	/
63	Synplicity was having troubles with the comment.	mohor	8187d 21h	/
62	Bug that was entered in the last update fixed (rx state machine).	mohor	8188d 20h	/
61	overrun signal was moved to separate block because many sequential lsr reads were preventing data from being written to rx fifo. underrun signal was not used and was removed from the project.	mohor	8189d 14h	/
60	Things related to msr register changed. After THRE IRQ occurs, and one character is written to the transmit fifo, the detection of the THRE bit in the LSR is delayed for one character time.	mohor	8189d 19h	/
59	MSR register fixed.	mohor	8192d 16h	/
58	After reset modem status register MSR should be reset.	mohor	8192d 19h	/
57	timeout irq must be set regardless of the rda irq (rda irq does not reset the timeout counter).	mohor	8193d 18h	/
56	thre irq should be cleared only when being source of interrupt.	mohor	8193d 19h	/
55	some synthesis bugs fixed	gorban	8194d 07h	/
54	LSR status bit 0 was not cleared correctly in case of reseting the FCR (rx fifo).	mohor	8194d 20h	/
53	Scratch register define added.	mohor	8195d 20h	/
52	Scratch register added	gorban	8196d 09h	/
51	Igor fixed break condition bugs	gorban	8196d 09h	/
50	Bug in LSR[0] is fixed. All WISHBONE signals are now sampled, so another wait-state is introduced on all transfers.	gorban	8200d 14h	/
49	committed the debug interface file	gorban	8202d 08h	/
48	Updated specification documentation. Added full 32-bit data bus interface, now as default. Address is 5-bit wide in 32-bit data bus mode. Added wb_sel_i input to the core. It's used in the 32-bit mode. Added debug interface with two 32-bit read-only registers in 32-bit mode. Bits 5 and 6 of LSR are now only cleared on TX FIFO write. My small test bench is modified to work with 32-bit mode.	gorban	8203d 07h	/
47	Fixed: timeout and break didn't pay attention to current data format when counting time	gorban	8208d 09h	/

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