URL https://opencores.org/ocsvn/uart16550/uart16550/trunk

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Rev	Log message	Author	Age	Path
78	This commit was manufactured by cvs2svn to create tag 'rel_1'.		8115d 00h	/
77	This commit was manufactured by cvs2svn to create tag 'asyst_3'.		8115d 00h	/
76	This commit was manufactured by cvs2svn to create tag 'asyst_2'.		8115d 00h	/
75	Endian define added. Big Byte Endian is selected by default.	mohor	8115d 00h	/
74	tf_overrun signal was disabled since it was not used	gorban	8120d 01h	/
73	major bug in 32-bit mode that prevented register access fixed.	gorban	8127d 00h	/
72	UART PHY added. Files are fully operational, working on HW.	mohor	8140d 08h	/
71	Removed confusing comment	gorban	8151d 20h	/
70	tf_pop was too wide. Now it is only 1 clk cycle width.	mohor	8157d 05h	/
69	More than one character was stored in case of break. End of the break was not detected correctly.	mohor	8165d 20h	/
68	lsr[7] was not showing overrun errors.	mohor	8169d 03h	/
67	Missing declaration of rf_push_q fixed.	mohor	8176d 03h	/
66	rx push changed to be only one cycle wide.	mohor	8176d 03h	/
65	Warnings fixed (unused signals removed).	mohor	8177d 08h	/
64	Warnings cleared.	mohor	8177d 09h	/
63	Synplicity was having troubles with the comment.	mohor	8177d 09h	/
62	Bug that was entered in the last update fixed (rx state machine).	mohor	8178d 08h	/
61	overrun signal was moved to separate block because many sequential lsr reads were preventing data from being written to rx fifo. underrun signal was not used and was removed from the project.	mohor	8179d 02h	/
60	Things related to msr register changed. After THRE IRQ occurs, and one character is written to the transmit fifo, the detection of the THRE bit in the LSR is delayed for one character time.	mohor	8179d 06h	/
59	MSR register fixed.	mohor	8182d 03h	/

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Subversion Repositories uart16550

[/] - Rev 78

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