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Rev	Log message	Author	Age	Path
78	This commit was manufactured by cvs2svn to create tag 'rel_1'.		8125d 16h	/
77	This commit was manufactured by cvs2svn to create tag 'asyst_3'.		8125d 16h	/
76	This commit was manufactured by cvs2svn to create tag 'asyst_2'.		8125d 16h	/
75	Endian define added. Big Byte Endian is selected by default.	mohor	8125d 16h	/
74	tf_overrun signal was disabled since it was not used	gorban	8130d 18h	/
73	major bug in 32-bit mode that prevented register access fixed.	gorban	8137d 17h	/
72	UART PHY added. Files are fully operational, working on HW.	mohor	8151d 00h	/
71	Removed confusing comment	gorban	8162d 13h	/
70	tf_pop was too wide. Now it is only 1 clk cycle width.	mohor	8167d 22h	/
69	More than one character was stored in case of break. End of the break was not detected correctly.	mohor	8176d 13h	/
68	lsr[7] was not showing overrun errors.	mohor	8179d 20h	/
67	Missing declaration of rf_push_q fixed.	mohor	8186d 20h	/
66	rx push changed to be only one cycle wide.	mohor	8186d 20h	/
65	Warnings fixed (unused signals removed).	mohor	8188d 01h	/
64	Warnings cleared.	mohor	8188d 01h	/
63	Synplicity was having troubles with the comment.	mohor	8188d 02h	/
62	Bug that was entered in the last update fixed (rx state machine).	mohor	8189d 00h	/
61	overrun signal was moved to separate block because many sequential lsr reads were preventing data from being written to rx fifo. underrun signal was not used and was removed from the project.	mohor	8189d 19h	/
60	Things related to msr register changed. After THRE IRQ occurs, and one character is written to the transmit fifo, the detection of the THRE bit in the LSR is delayed for one character time.	mohor	8189d 23h	/
59	MSR register fixed.	mohor	8192d 20h	/
58	After reset modem status register MSR should be reset.	mohor	8192d 23h	/
57	timeout irq must be set regardless of the rda irq (rda irq does not reset the timeout counter).	mohor	8193d 23h	/
56	thre irq should be cleared only when being source of interrupt.	mohor	8193d 23h	/
55	some synthesis bugs fixed	gorban	8194d 11h	/
54	LSR status bit 0 was not cleared correctly in case of reseting the FCR (rx fifo).	mohor	8195d 00h	/
53	Scratch register define added.	mohor	8196d 00h	/
52	Scratch register added	gorban	8196d 13h	/
51	Igor fixed break condition bugs	gorban	8196d 13h	/
50	Bug in LSR[0] is fixed. All WISHBONE signals are now sampled, so another wait-state is introduced on all transfers.	gorban	8200d 18h	/
49	committed the debug interface file	gorban	8202d 12h	/

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