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Rev Log message Author Age Path
58 After reset modem status register MSR should be reset. mohor 8204d 13h /
57 timeout irq must be set regardless of the rda irq (rda irq does not reset the
timeout counter).
mohor 8205d 13h /
56 thre irq should be cleared only when being source of interrupt. mohor 8205d 13h /
55 some synthesis bugs fixed gorban 8206d 01h /
54 LSR status bit 0 was not cleared correctly in case of reseting the FCR (rx fifo). mohor 8206d 14h /
53 Scratch register define added. mohor 8207d 14h /
52 Scratch register added gorban 8208d 04h /
51 Igor fixed break condition bugs gorban 8208d 04h /
50 Bug in LSR[0] is fixed.
All WISHBONE signals are now sampled, so another wait-state is introduced on all transfers.
gorban 8212d 09h /
49 committed the debug interface file gorban 8214d 02h /

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