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Subversion Repositories uart16750

[/] [uart16750/] [trunk/] - Rev 25

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Rev Log message Author Age Path
25 UART16750: Updated testbench hasw 5037d 05h /uart16750/trunk/
24 Inverted low active outputs when RST is active hasw 5037d 05h /uart16750/trunk/
23 Fixed paths in Makefile for simulation hasw 5401d 08h /uart16750/trunk/
22 Removed old stimuli data file, created by perl script hasw 5401d 08h /uart16750/trunk/
21 Updated simulation files hasw 5401d 08h /uart16750/trunk/
20 UART16750: Check only half of the stop bit in the receiver to resume faster to the IDLE state hasw 5531d 06h /uart16750/trunk/
17 New directory structure. root 5547d 16h /uart16750/trunk/
16 UART16750: Added example project hasw 5568d 03h /trunk/
15 UART16750: Decreased input filter size. De-assert IIR FIFO64 when FIFO is disabled. Fixed typo. Added FIFO 64 tests. hasw 5577d 05h /trunk/
14 UART16750: Decreased input filter size. De-assert IIR FIFO64 when FIFO is disabled. Fixed typo. Added FIFO 64 tests. hasw 5578d 07h /trunk/
13 UART16750: Added automatic flow control hasw 5591d 08h /trunk/
12 UART16750: Updated stimuli script with automatic flow control tests hasw 5591d 08h /trunk/
11 UART16750: Removed dependency from std_logic_unsigned hasw 5591d 08h /trunk/
10 UART16750: Removed dependency from std_logic_unsigned hasw 5591d 09h /trunk/
9 Registered control line outputs hasw 5600d 10h /trunk/
8 Make memory read in generic FIFO model synchronous for optimized used with XST hasw 5600d 10h /trunk/
7 Removed async. reset of FIFO memory cells for optimized usage of default FIFO model with XST hasw 5601d 15h /trunk/
6 THR empty interrupt register connected to RST hasw 5601d 16h /trunk/
5 Removed old component hasw 5602d 10h /trunk/
4 Removed swap file hasw 5602d 11h /trunk/
2 Imported sources hasw 5602d 11h /trunk/
1 Standard project directories initialized by cvs2svn. 5602d 11h /trunk/

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