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Rev Log message Author Age Path
17 New directory structure. root 5547d 16h /
16 UART16750: Added example project hasw 5568d 03h /
15 UART16750: Decreased input filter size. De-assert IIR FIFO64 when FIFO is disabled. Fixed typo. Added FIFO 64 tests. hasw 5577d 05h /
14 UART16750: Decreased input filter size. De-assert IIR FIFO64 when FIFO is disabled. Fixed typo. Added FIFO 64 tests. hasw 5578d 07h /
13 UART16750: Added automatic flow control hasw 5591d 08h /
12 UART16750: Updated stimuli script with automatic flow control tests hasw 5591d 08h /
11 UART16750: Removed dependency from std_logic_unsigned hasw 5591d 08h /
10 UART16750: Removed dependency from std_logic_unsigned hasw 5591d 09h /
9 Registered control line outputs hasw 5600d 10h /
8 Make memory read in generic FIFO model synchronous for optimized used with XST hasw 5600d 10h /
7 Removed async. reset of FIFO memory cells for optimized usage of default FIFO model with XST hasw 5601d 15h /
6 THR empty interrupt register connected to RST hasw 5601d 16h /
5 Removed old component hasw 5602d 10h /
4 Removed swap file hasw 5602d 11h /
3 This commit was manufactured by cvs2svn to create tag 'Import'. 5602d 11h /
2 Imported sources hasw 5602d 11h /
1 Standard project directories initialized by cvs2svn. 5602d 11h /

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