URL https://opencores.org/ocsvn/uart2bus/uart2bus/trunk

Subversion Repositories uart2bus

[/] - Rev 7

Rev	Log message	Author	Age	Path
7	Updated the Scilab script for Scilab 5.3 version. Previous versions might not work.	motilito	4811d 09h	/
6	Commit VHDL description source with basic test benches	smuller	5060d 18h	/
5	Add structure for VHDL (verilog similar tree).	smuller	5072d 12h	/
4	Corrected some problems in the binary mode protocol test bench. Updated documentation.	motilito	5167d 10h	/
3		motilito	5213d 16h	/
2	Uploaded the initial project version.	motilito	5213d 17h	/
1	The project and the structure was created	root	5216d 11h	/