URL https://opencores.org/ocsvn/uart_fifo_cpu_if_sv_testbench/uart_fifo_cpu_if_sv_testbench/trunk

Subversion Repositories uart_fifo_cpu_if_sv_testbench

[/] [uart_fifo_cpu_if_sv_testbench/] - Rev 4

Rev	Log message	Author	Age	Path
4	Several SV testbench fixes. Testbench and DUT now elaborate sucessfully in the simulator.	andrewbridger	4867d 07h	/uart_fifo_cpu_if_sv_testbench/
3	Changed to send and receive least significant bit first.	andrewbridger	4867d 18h	/uart_fifo_cpu_if_sv_testbench/
2	Added complete UART RTL and testbench. Both compile, but not debugged in simulator yet. Synchronous FIFO yet to be added. File headers need tidying.	andrewbridger	4868d 05h	/uart_fifo_cpu_if_sv_testbench/
1	The project and the structure was created	root	4868d 06h	/uart_fifo_cpu_if_sv_testbench/