URL https://opencores.org/ocsvn/uart_fifo_cpu_if_sv_testbench/uart_fifo_cpu_if_sv_testbench/trunk

Subversion Repositories uart_fifo_cpu_if_sv_testbench

[/] [uart_fifo_cpu_if_sv_testbench/] [trunk/] [bench/] [uart_tb.sv] - Rev 4

Rev	Log message	Author	Age	Path
4	Several SV testbench fixes. Testbench and DUT now elaborate sucessfully in the simulator.	andrewbridger	4882d 13h	/uart_fifo_cpu_if_sv_testbench/trunk/bench/uart_tb.sv
3	Changed to send and receive least significant bit first.	andrewbridger	4883d 00h	/uart_fifo_cpu_if_sv_testbench/trunk/bench/uart_tb.sv
2	Added complete UART RTL and testbench. Both compile, but not debugged in simulator yet. Synchronous FIFO yet to be added. File headers need tidying.	andrewbridger	4883d 12h	/uart_fifo_cpu_if_sv_testbench/trunk/bench/uart_tb.sv