URL https://opencores.org/ocsvn/usb_phy/usb_phy/trunk

Subversion Repositories usb_phy

[/] [usb_phy/] [trunk/] [rtl/] [verilog/] - Rev 12

Rev	Log message	Author	Age	Path
12	New directory structure.	root	5548d 14h	/usb_phy/trunk/rtl/verilog/
11	Fixed DPLL alignment in the rx_phy and bit stuffing errors in the tx_phy (if last bit bit was a stuff bit in a packet it was omitted).	rudi	7151d 15h	/usb_phy/trunk/rtl/verilog/
10	Fixed a bug reported by Karl C. Posch from Graz University of Technology. Thanks Karl !	rudi	7473d 20h	/usb_phy/trunk/rtl/verilog/
9	usb_rst is no longer or'ed with the incomming reset internally. Now usb_rst is simply an output, the application can decide how to utilize it.	rudi	7515d 19h	/usb_phy/trunk/rtl/verilog/
8	- Fixed Sync Error to be only checked/generated during the sync phase	rudi	7517d 07h	/usb_phy/trunk/rtl/verilog/
7	- Made core more robust against line noise - Added Error Checking and Reporting (See README.txt for more info)	rudi	7517d 07h	/usb_phy/trunk/rtl/verilog/
4	Changed top level name to be consistent ...	rudi	7915d 09h	/usb_phy/trunk/rtl/verilog/
2	Created Directory Structure	rudi	7915d 10h	/usb_phy/trunk/rtl/verilog/