URL https://opencores.org/ocsvn/versatile_fifo/versatile_fifo/trunk

Subversion Repositories versatile_fifo

[/] - Rev 32

Rev	Log message	Author	Age	Path
32	fixed SYN directives	marcus.erlandsson	4939d 06h	/
31	port map	unneback	5009d 23h	/
30	port map	unneback	5010d 00h	/
29	ACTEL syn define	unneback	5017d 21h	/
28	ACTEL async dual way FIFO	unneback	5025d 07h	/
27	initial commit, dual way simplex FIFO	unneback	5025d 22h	/
26	added ACTEL synthesis directive as define, +ACTEL	unneback	5025d 22h	/
25	DFF SR as separate logic	unneback	5165d 18h	/
24	updated fifo interfaces with re/rd and we/wr	unneback	5166d 08h	/
23		unneback	5168d 21h	/
22	async fifo with multiple queues	unneback	5168d 21h	/
21	added DFF SR	unneback	5182d 19h	/
20		unneback	5183d 02h	/
19	DFF with async clear and set for Altera cycloneIV	unneback	5184d 08h	/
18	ADDR and DATA width set to 8 resp 32	unneback	5184d 22h	/
17	based on updated versatile counter	unneback	5188d 20h	/
16	changed power of two style	unneback	5452d 06h	/
15	doc updated gray_counter_defines added dual port RAM updated	unneback	5456d 00h	/
14	added PDF	unneback	5500d 06h	/
13	adr update	unneback	5501d 08h	/
12	no mux on dual port mem read	unneback	5514d 02h	/
11	name conflict wptr1 changed to wptr1_cnt etc	unneback	5514d 04h	/
10	rptr2	unneback	5514d 06h	/
9		unneback	5520d 01h	/
8		unneback	5520d 01h	/
7		unneback	5520d 01h	/
6		unneback	5520d 04h	/
5	async compare for fifo full and empty	unneback	5520d 04h	/
4		unneback	5520d 08h	/
3		unneback	5520d 09h	/