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URL https://opencores.org/ocsvn/virtex7_pcie_dma/virtex7_pcie_dma/trunk

Subversion Repositories virtex7_pcie_dma

[/] [virtex7_pcie_dma/] - Rev 32

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Rev Log message Author Age Path
32 MODIFIED:
-- minor things just to test OC svn repo		 aborga 2936d 19h /virtex7_pcie_dma/
31 Added example application documentation. oussamak 3030d 21h /virtex7_pcie_dma/
30 Added:
* Wupper GUI with speed test and chain test
* Added wupper-dma-transfer, wupper-chaintest and wupper-write
* Several bug fixes in the Wupper tools		 oussamak 3030d 21h /virtex7_pcie_dma/
29 Improved application to reflect both up and down transfers fransschreuder 3072d 19h /virtex7_pcie_dma/
28 Added registermap reset fransschreuder 3072d 21h /virtex7_pcie_dma/
27 Fixed:
* BUG 2580: Missing packets in receive (PC => FPGA) path

Changed:
* Client tags now handled by Xilinx IP core
* fifo signals to reflect upfifo and downfifo naming		 fransschreuder 3073d 00h /virtex7_pcie_dma/
26 Added sys_clk constraint fransschreuder 3073d 02h /virtex7_pcie_dma/
25 Added scripts and constraints for KCU105 fransschreuder 3073d 03h /virtex7_pcie_dma/
24 Added:
* Support for KCU105 board in code
TODO
* Add constraints and build scripts for KCU105		 fransschreuder 3073d 20h /virtex7_pcie_dma/
23 Fixed reset of application registers fransschreuder 3131d 02h /virtex7_pcie_dma/
22 Added dma_soft_reset to trigger register resets fransschreuder 3137d 01h /virtex7_pcie_dma/
21 Fixed BUG http://opencores.org/bug,view,2562 fransschreuder 3145d 23h /virtex7_pcie_dma/
20 Fixed:
* Missing packets if the fifo goes empty during a TLP
* Dynamically change the empty threshold of the main fifo to TLP size		 fransschreuder 3159d 21h /virtex7_pcie_dma/
19 * driver/README updated oussamak 3165d 23h /virtex7_pcie_dma/
18 Changed:
* Added drivers
* Added Wupper tools for debugging
* Added card ID register		 oussamak 3166d 01h /virtex7_pcie_dma/
17 Changed name of toplevel, to make tree consistent oussamak 3180d 03h /virtex7_pcie_dma/
16 MODIFED:
-- top level name to wupper_oc (including scripts)		 aborga 3229d 21h /virtex7_pcie_dma/
15 MODIFIED:
-- Renamed core to Wupper (vhdl files)
-- Changed width of interrupt enable to number_of_interrupts		 fransschreuder 3229d 22h /virtex7_pcie_dma/
14 RENAMED:
-- simulation folder		 aborga 3229d 23h /virtex7_pcie_dma/
13 RENAMED:
-- script		 aborga 3229d 23h /virtex7_pcie_dma/

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