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[/] [virtex7_pcie_dma/] - Rev 45

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Rev Log message Author Age Path
45 Fixed duplicate driver and Vivado 2018.1 PCIe core fransschreuder 1853d 03h /virtex7_pcie_dma/
44 EDITED: added image size aborga 1940d 18h /virtex7_pcie_dma/
43 ADDED: README.md to be parsed by the OC project page aborga 1941d 00h /virtex7_pcie_dma/
42 Added filter in wuppercodegen in order to generate 2d arrays of registers fransschreuder 2285d 23h /virtex7_pcie_dma/
41 Added brief description of Wishbone broel 2385d 23h /virtex7_pcie_dma/
40 Updated comment header for syscon. broel 2386d 01h /virtex7_pcie_dma/
39 Added Wishbone bus to Wupper plus a Wishbone memory as an example. broel 2389d 19h /virtex7_pcie_dma/
38 Fixed include of stdint.h broel 2398d 02h /virtex7_pcie_dma/
37 * Added WupperCodeGen, a tool to generate the registermap vhdl, c++ and latex doc from a single .YAML file
* Fixed bug: crash when polling enable bits while transferring DMA in two directions at the same time
* Code cleanup
* Updated documentation with WupperCodeGen		 fransschreuder 2398d 19h /virtex7_pcie_dma/
36 Updated documentation fransschreuder 2733d 20h /virtex7_pcie_dma/
35 FIXED:
* PCIe lock when reading registers on a high frequency
* Added threshold registers for Prog Full of the FromHost fifo
* Code cleanup		 fransschreuder 2788d 00h /virtex7_pcie_dma/
34 FIXED:
* Wrong TLP length reported on register writes
* Two simultaneous interrupts were not handled
* XADC wizard for ultrascale devices

Added:
* Added voltage (int, aux, bram) readout on XADC wizards		 fransschreuder 2893d 19h /virtex7_pcie_dma/
33 ADDED:
-- supportedtools.tex, again to test the OC repo		 aborga 2938d 18h /virtex7_pcie_dma/
32 MODIFIED:
-- minor things just to test OC svn repo		 aborga 2938d 18h /virtex7_pcie_dma/
31 Added example application documentation. oussamak 3032d 20h /virtex7_pcie_dma/
30 Added:
* Wupper GUI with speed test and chain test
* Added wupper-dma-transfer, wupper-chaintest and wupper-write
* Several bug fixes in the Wupper tools		 oussamak 3032d 20h /virtex7_pcie_dma/
29 Improved application to reflect both up and down transfers fransschreuder 3074d 18h /virtex7_pcie_dma/
28 Added registermap reset fransschreuder 3074d 20h /virtex7_pcie_dma/
27 Fixed:
* BUG 2580: Missing packets in receive (PC => FPGA) path

Changed:
* Client tags now handled by Xilinx IP core
* fifo signals to reflect upfifo and downfifo naming		 fransschreuder 3074d 23h /virtex7_pcie_dma/
26 Added sys_clk constraint fransschreuder 3075d 01h /virtex7_pcie_dma/

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