OpenCores
URL https://opencores.org/ocsvn/virtex7_pcie_dma/virtex7_pcie_dma/trunk

Subversion Repositories virtex7_pcie_dma

[/] [virtex7_pcie_dma/] - Rev 47

Rev

Filtering Options

Clear current filter

Rev Log message Author Age Path
47 Deleted all files, the repository was moved to Nikhef Gitlab, files will come back to OpenCores when it supports git. fransschreuder 965d 04h /virtex7_pcie_dma/
46 New Vivado version, changed regmap clock, added byte enable to regmap
* Updated wupper for Vivado 2018.1
* Byte enable on registermap is now supported
* Fixed i2c mux reset (inversion) on VC709 board
* Regmap is now running on 25 MHz for better timing, this was 41.6 MHz
* registers can now be disabled at build time using the generate statement in the .yaml file
fransschreuder 1812d 02h /virtex7_pcie_dma/
45 Fixed duplicate driver and Vivado 2018.1 PCIe core fransschreuder 1836d 10h /virtex7_pcie_dma/
44 EDITED: added image size aborga 1924d 02h /virtex7_pcie_dma/
43 ADDED: README.md to be parsed by the OC project page aborga 1924d 07h /virtex7_pcie_dma/
42 Added filter in wuppercodegen in order to generate 2d arrays of registers fransschreuder 2269d 07h /virtex7_pcie_dma/
41 Added brief description of Wishbone broel 2369d 06h /virtex7_pcie_dma/
40 Updated comment header for syscon. broel 2369d 08h /virtex7_pcie_dma/
39 Added Wishbone bus to Wupper plus a Wishbone memory as an example. broel 2373d 02h /virtex7_pcie_dma/
38 Fixed include of stdint.h broel 2381d 09h /virtex7_pcie_dma/
37 * Added WupperCodeGen, a tool to generate the registermap vhdl, c++ and latex doc from a single .YAML file
* Fixed bug: crash when polling enable bits while transferring DMA in two directions at the same time
* Code cleanup
* Updated documentation with WupperCodeGen
fransschreuder 2382d 02h /virtex7_pcie_dma/
36 Updated documentation fransschreuder 2717d 03h /virtex7_pcie_dma/
35 FIXED:
* PCIe lock when reading registers on a high frequency
* Added threshold registers for Prog Full of the FromHost fifo
* Code cleanup
fransschreuder 2771d 07h /virtex7_pcie_dma/
34 FIXED:
* Wrong TLP length reported on register writes
* Two simultaneous interrupts were not handled
* XADC wizard for ultrascale devices

Added:
* Added voltage (int, aux, bram) readout on XADC wizards
fransschreuder 2877d 02h /virtex7_pcie_dma/
33 ADDED:
-- supportedtools.tex, again to test the OC repo
aborga 2922d 01h /virtex7_pcie_dma/
32 MODIFIED:
-- minor things just to test OC svn repo
aborga 2922d 01h /virtex7_pcie_dma/
31 Added example application documentation. oussamak 3016d 03h /virtex7_pcie_dma/
30 Added:
* Wupper GUI with speed test and chain test
* Added wupper-dma-transfer, wupper-chaintest and wupper-write
* Several bug fixes in the Wupper tools
oussamak 3016d 04h /virtex7_pcie_dma/
29 Improved application to reflect both up and down transfers fransschreuder 3058d 01h /virtex7_pcie_dma/
28 Added registermap reset fransschreuder 3058d 03h /virtex7_pcie_dma/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.