OpenCores
URL https://opencores.org/ocsvn/wb2axip/wb2axip/trunk

Subversion Repositories wb2axip

[/] - Rev 18

Rev

Filtering Options

Clear current filter

Rev Log message Author Age Path
18 Updated svn:ignore properties dgisselq 1866d 21h /
17 Updating svn:ignore properties dgisselq 1866d 21h /
16 Lots of updates (see below)

New files:
1. AXI-lite formal checker(s)
2. AXI-lite to WB bridge
3. WB to AXI-lite bridge
4. WB cross bar (for lack of a better place)
5. Demonstration/example AXI-lite core

Other files have been updated as necessary. Ex. the WB formal checker files.		 dgisselq 1870d 07h /
15 Quick update, making this module verilatable again dgisselq 2230d 10h /
14 Added a reset line upon user request dgisselq 2230d 10h /
13 Bug fix release--fixes the bugs Antti pointed out. dgisselq 2243d 00h /
12 Added Verilators obj_dir to the list of ignored files dgisselq 2340d 11h /
11 Updated the bench/formal properties

SVN will now ignore the build files associated with this directory: *.smt2,
*.yslog, *.vcd		 dgisselq 2340d 11h /
10 Added files to flush out the formal proof capability dgisselq 2340d 12h /
9 Added a formal directory dgisselq 2340d 12h /
8 The WB to AXI translator wrks and works well.

A proof of this will be added shortly.		 dgisselq 2340d 12h /
7 Simplified. dgisselq 2657d 12h /
6 IT WORKS!!! (On non-pipelined data--havent tested it on pipelined stuff .. yet) dgisselq 2785d 07h /
5 Adjusted variable names to match the spec and the MIG. dgisselq 2789d 22h /
4 Adjusted the core quickly so it should work for 128-bit wide wishbone busses
as well as 32-bit wide busses.		 dgisselq 2790d 04h /
3 Fixed the Verilator compile-time bugs. Still haven't tested the core. dgisselq 2790d 04h /
2 Initial check in. Core not (yet) tested, verified, or validated. dgisselq 2790d 05h /
1 The project and the structure was created root 2790d 05h /

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.