OpenCores
URL https://opencores.org/ocsvn/wbuart32/wbuart32/trunk

Subversion Repositories wbuart32

[/] [wbuart32/] [trunk/] - Rev 26

Rev

Filtering Options

Clear current filter

Rev Log message Author Age Path
26 Formally verified the TXUART core (plus others) dgisselq 1872d 13h /wbuart32/trunk/
25 dgisselq 2073d 22h /wbuart32/trunk/
24 Fixed the broken TX interrupt flagg dgisselq 2073d 23h /wbuart32/trunk/
23 Brought SVN repo up to date with github repo dgisselq 2073d 23h /wbuart32/trunk/
22 Added formal methods via SymbiYosys dgisselq 2165d 21h /wbuart32/trunk/
21 Updates based upon Formal methods dgisselq 2165d 21h /wbuart32/trunk/
20 Added yosys-smtbmc config files for formal proofs dgisselq 2360d 17h /wbuart32/trunk/
19 Added a directory for formal info dgisselq 2360d 17h /wbuart32/trunk/
18 Lots of updates. See the git log for details dgisselq 2360d 17h /wbuart32/trunk/
17 Biggest change: default_nettype

Also fixed potential ufifo overload condition, and wbuart not calling
txuartlite when so instructed.
dgisselq 2568d 19h /wbuart32/trunk/
16 Updated the property list for cpp directory. dgisselq 2593d 00h /wbuart32/trunk/
15 Added a set of lite-UARTs that only handle 8N1 to the repository. dgisselq 2593d 00h /wbuart32/trunk/
14 This version works on hardware. dgisselq 2628d 02h /wbuart32/trunk/
13 Adjusted documentation of OPT_STANDALONE, and updated internal README files. dgisselq 2628d 22h /wbuart32/trunk/
12 Added hardware flow control information to the specification. dgisselq 2628d 22h /wbuart32/trunk/
11 Modified mkspeech to create both hex and include files, to tailor for the broken ISE program. dgisselq 2628d 23h /wbuart32/trunk/
10 Adjusted for the new hardware flow control capability. dgisselq 2628d 23h /wbuart32/trunk/
9 Added a hardware flow control capability. dgisselq 2628d 23h /wbuart32/trunk/
8 Updated the documents to reference the new testbenches. dgisselq 2660d 02h /wbuart32/trunk/
7 Moved the definition of state to before its first usage. dgisselq 2660d 02h /wbuart32/trunk/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.