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Rev Log message Author Age Path
15 Updated for Verilator 3.813 antanguay 4682d 06h /
14 Change interface to big endian, added serdes examples to testbench antanguay 5271d 00h /
13 Change interface to big endian, added serdes examples to testbench antanguay 5271d 01h /
12 Change interface to big endian, added serdes examples to testbench antanguay 5271d 01h /
11 Fixed clock crossing antanguay 5376d 22h /
10 Added details to spec antanguay 5474d 17h /
9 Added old uploaded documents to new repository. root 5549d 05h /
8 Added old uploaded documents to new repository. root 5549d 10h /
7 New directory structure. root 5549d 10h /
6 Updated spec. Added mod[2:0] signals. Timing improvements. antanguay 5825d 18h /
5 Fixed compilation antanguay 5831d 18h /
4 Created antanguay 5831d 21h /
3 This commit was manufactured by cvs2svn to create tag 'initial'. 5831d 22h /
2 Initial revision antanguay 5831d 22h /
1 Standard project directories initialized by cvs2svn. 5831d 22h /

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