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Rev Log message Author Age Path
21 Improvements for timing, adding alternate FIFO design using XIL define antanguay 4195d 01h /
20 Updates for Xilinx synthesis antanguay 4484d 19h /
19 Updates for 32/64 bit systems antanguay 4659d 20h /
18 Updates for linux 32-bit antanguay 4660d 17h /
17 Fixed deprecated SystemC warnings antanguay 4663d 01h /
16 Rename tb_xge_mac.v to sv extension to fix issue with newer Modelsim antanguay 4663d 07h /
15 Updated for Verilator 3.813 antanguay 4682d 08h /
14 Change interface to big endian, added serdes examples to testbench antanguay 5271d 02h /
13 Change interface to big endian, added serdes examples to testbench antanguay 5271d 03h /
12 Change interface to big endian, added serdes examples to testbench antanguay 5271d 03h /
11 Fixed clock crossing antanguay 5377d 00h /
10 Added details to spec antanguay 5474d 19h /
9 Added old uploaded documents to new repository. root 5549d 07h /
8 Added old uploaded documents to new repository. root 5549d 12h /
7 New directory structure. root 5549d 12h /
6 Updated spec. Added mod[2:0] signals. Timing improvements. antanguay 5825d 20h /
5 Fixed compilation antanguay 5831d 20h /
4 Created antanguay 5831d 23h /
3 This commit was manufactured by cvs2svn to create tag 'initial'. 5832d 00h /
2 Initial revision antanguay 5832d 00h /

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