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Rev Log message Author Age Path
27 Fix octets stats on barrel shift transitions antanguay 4186d 14h /
26 Fix packet count antanguay 4192d 15h /
25 Timing improvements, reduced FIFO size from 1024 to 512 antanguay 4192d 16h /
24 Use FIFO's for statistics clock domain crossing antanguay 4192d 18h /
23 Adding basic packet stats antanguay 4193d 00h /
22 Added prototype system verilog testbench antanguay 4194d 20h /
21 Improvements for timing, adding alternate FIFO design using XIL define antanguay 4194d 21h /
20 Updates for Xilinx synthesis antanguay 4484d 15h /
19 Updates for 32/64 bit systems antanguay 4659d 16h /
18 Updates for linux 32-bit antanguay 4660d 13h /
17 Fixed deprecated SystemC warnings antanguay 4662d 21h /
16 Rename tb_xge_mac.v to sv extension to fix issue with newer Modelsim antanguay 4663d 03h /
15 Updated for Verilator 3.813 antanguay 4682d 03h /
14 Change interface to big endian, added serdes examples to testbench antanguay 5270d 22h /
13 Change interface to big endian, added serdes examples to testbench antanguay 5270d 22h /
12 Change interface to big endian, added serdes examples to testbench antanguay 5270d 23h /
11 Fixed clock crossing antanguay 5376d 20h /
10 Added details to spec antanguay 5474d 15h /
9 Added old uploaded documents to new repository. root 5549d 03h /
8 Added old uploaded documents to new repository. root 5549d 08h /

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