URL https://opencores.org/ocsvn/xge_mac/xge_mac/trunk

Subversion Repositories xge_mac

[/] [xge_mac/] - Rev 28

Rev	Log message	Author	Age	Path
28	Adding parameter for max frame size	antanguay	4147d 15h	/xge_mac/
27	Fix octets stats on barrel shift transitions	antanguay	4196d 14h	/xge_mac/
26	Fix packet count	antanguay	4202d 15h	/xge_mac/
25	Timing improvements, reduced FIFO size from 1024 to 512	antanguay	4202d 16h	/xge_mac/
24	Use FIFO's for statistics clock domain crossing	antanguay	4202d 18h	/xge_mac/
23	Adding basic packet stats	antanguay	4203d 00h	/xge_mac/
22	Added prototype system verilog testbench	antanguay	4204d 20h	/xge_mac/
21	Improvements for timing, adding alternate FIFO design using XIL define	antanguay	4204d 21h	/xge_mac/
20	Updates for Xilinx synthesis	antanguay	4494d 15h	/xge_mac/
19	Updates for 32/64 bit systems	antanguay	4669d 16h	/xge_mac/
18	Updates for linux 32-bit	antanguay	4670d 13h	/xge_mac/
17	Fixed deprecated SystemC warnings	antanguay	4672d 21h	/xge_mac/
16	Rename tb_xge_mac.v to sv extension to fix issue with newer Modelsim	antanguay	4673d 03h	/xge_mac/
15	Updated for Verilator 3.813	antanguay	4692d 03h	/xge_mac/
14	Change interface to big endian, added serdes examples to testbench	antanguay	5280d 22h	/xge_mac/
13	Change interface to big endian, added serdes examples to testbench	antanguay	5280d 22h	/xge_mac/
12	Change interface to big endian, added serdes examples to testbench	antanguay	5280d 23h	/xge_mac/
11	Fixed clock crossing	antanguay	5386d 20h	/xge_mac/
10	Added details to spec	antanguay	5484d 15h	/xge_mac/
9	Added old uploaded documents to new repository.	root	5559d 02h	/xge_mac/