URL https://opencores.org/ocsvn/xge_mac/xge_mac/trunk

Subversion Repositories xge_mac

[/] [xge_mac/] [trunk/] - Rev 23

Rev	Log message	Author	Age	Path
23	Adding basic packet stats	antanguay	4204d 07h	/xge_mac/trunk/
22	Added prototype system verilog testbench	antanguay	4206d 04h	/xge_mac/trunk/
21	Improvements for timing, adding alternate FIFO design using XIL define	antanguay	4206d 04h	/xge_mac/trunk/
20	Updates for Xilinx synthesis	antanguay	4495d 22h	/xge_mac/trunk/
19	Updates for 32/64 bit systems	antanguay	4671d 00h	/xge_mac/trunk/
18	Updates for linux 32-bit	antanguay	4671d 20h	/xge_mac/trunk/
17	Fixed deprecated SystemC warnings	antanguay	4674d 04h	/xge_mac/trunk/
16	Rename tb_xge_mac.v to sv extension to fix issue with newer Modelsim	antanguay	4674d 10h	/xge_mac/trunk/
15	Updated for Verilator 3.813	antanguay	4693d 11h	/xge_mac/trunk/
14	Change interface to big endian, added serdes examples to testbench	antanguay	5282d 05h	/xge_mac/trunk/
13	Change interface to big endian, added serdes examples to testbench	antanguay	5282d 06h	/xge_mac/trunk/
12	Change interface to big endian, added serdes examples to testbench	antanguay	5282d 06h	/xge_mac/trunk/
11	Fixed clock crossing	antanguay	5388d 03h	/xge_mac/trunk/
10	Added details to spec	antanguay	5485d 22h	/xge_mac/trunk/
7	New directory structure.	root	5560d 15h	/xge_mac/trunk/
6	Updated spec. Added mod[2:0] signals. Timing improvements.	antanguay	5836d 23h	/trunk/
5	Fixed compilation	antanguay	5842d 23h	/trunk/
4	Created	antanguay	5843d 02h	/trunk/
2	Initial revision	antanguay	5843d 03h	/trunk/
1	Standard project directories initialized by cvs2svn.		5843d 03h	/trunk/