URL https://opencores.org/ocsvn/xge_mac/xge_mac/trunk

Subversion Repositories xge_mac

[/] [xge_mac/] [trunk/] - Rev 24

Rev	Log message	Author	Age	Path
24	Use FIFO's for statistics clock domain crossing	antanguay	4204d 21h	/xge_mac/trunk/
23	Adding basic packet stats	antanguay	4205d 03h	/xge_mac/trunk/
22	Added prototype system verilog testbench	antanguay	4207d 00h	/xge_mac/trunk/
21	Improvements for timing, adding alternate FIFO design using XIL define	antanguay	4207d 00h	/xge_mac/trunk/
20	Updates for Xilinx synthesis	antanguay	4496d 18h	/xge_mac/trunk/
19	Updates for 32/64 bit systems	antanguay	4671d 19h	/xge_mac/trunk/
18	Updates for linux 32-bit	antanguay	4672d 16h	/xge_mac/trunk/
17	Fixed deprecated SystemC warnings	antanguay	4675d 00h	/xge_mac/trunk/
16	Rename tb_xge_mac.v to sv extension to fix issue with newer Modelsim	antanguay	4675d 06h	/xge_mac/trunk/
15	Updated for Verilator 3.813	antanguay	4694d 07h	/xge_mac/trunk/
14	Change interface to big endian, added serdes examples to testbench	antanguay	5283d 01h	/xge_mac/trunk/
13	Change interface to big endian, added serdes examples to testbench	antanguay	5283d 02h	/xge_mac/trunk/
12	Change interface to big endian, added serdes examples to testbench	antanguay	5283d 02h	/xge_mac/trunk/
11	Fixed clock crossing	antanguay	5388d 23h	/xge_mac/trunk/
10	Added details to spec	antanguay	5486d 18h	/xge_mac/trunk/
7	New directory structure.	root	5561d 11h	/xge_mac/trunk/
6	Updated spec. Added mod[2:0] signals. Timing improvements.	antanguay	5837d 19h	/trunk/
5	Fixed compilation	antanguay	5843d 19h	/trunk/
4	Created	antanguay	5843d 22h	/trunk/
2	Initial revision	antanguay	5843d 23h	/trunk/