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[/] [xge_mac/] [trunk/] - Rev 26

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Rev Log message Author Age Path
26 Fix packet count antanguay 4193d 04h /xge_mac/trunk/
25 Timing improvements, reduced FIFO size from 1024 to 512 antanguay 4193d 06h /xge_mac/trunk/
24 Use FIFO's for statistics clock domain crossing antanguay 4193d 08h /xge_mac/trunk/
23 Adding basic packet stats antanguay 4193d 13h /xge_mac/trunk/
22 Added prototype system verilog testbench antanguay 4195d 10h /xge_mac/trunk/
21 Improvements for timing, adding alternate FIFO design using XIL define antanguay 4195d 10h /xge_mac/trunk/
20 Updates for Xilinx synthesis antanguay 4485d 05h /xge_mac/trunk/
19 Updates for 32/64 bit systems antanguay 4660d 06h /xge_mac/trunk/
18 Updates for linux 32-bit antanguay 4661d 02h /xge_mac/trunk/
17 Fixed deprecated SystemC warnings antanguay 4663d 10h /xge_mac/trunk/
16 Rename tb_xge_mac.v to sv extension to fix issue with newer Modelsim antanguay 4663d 17h /xge_mac/trunk/
15 Updated for Verilator 3.813 antanguay 4682d 17h /xge_mac/trunk/
14 Change interface to big endian, added serdes examples to testbench antanguay 5271d 12h /xge_mac/trunk/
13 Change interface to big endian, added serdes examples to testbench antanguay 5271d 12h /xge_mac/trunk/
12 Change interface to big endian, added serdes examples to testbench antanguay 5271d 12h /xge_mac/trunk/
11 Fixed clock crossing antanguay 5377d 10h /xge_mac/trunk/
10 Added details to spec antanguay 5475d 05h /xge_mac/trunk/
7 New directory structure. root 5549d 22h /xge_mac/trunk/
6 Updated spec. Added mod[2:0] signals. Timing improvements. antanguay 5826d 05h /trunk/
5 Fixed compilation antanguay 5832d 06h /trunk/

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