URL https://opencores.org/ocsvn/xge_mac/xge_mac/trunk

Subversion Repositories xge_mac

[/] [xge_mac/] [trunk/] [rtl/] [verilog/] [generic_mem_small.v] - Rev 21

Rev	Log message	Author	Age	Path
21	Improvements for timing, adding alternate FIFO design using XIL define	antanguay	4195d 01h	/xge_mac/trunk/rtl/verilog/generic_mem_small.v
20	Updates for Xilinx synthesis	antanguay	4484d 19h	/xge_mac/trunk/rtl/verilog/generic_mem_small.v
7	New directory structure.	root	5549d 12h	/xge_mac/trunk/rtl/verilog/generic_mem_small.v
2	Initial revision	antanguay	5832d 00h	/xge_mac/trunk/rtl/verilog/generic_mem_small.v