URL https://opencores.org/ocsvn/xge_mac/xge_mac/trunk

Subversion Repositories xge_mac

[/] [xge_mac/] [trunk/] [rtl/] [verilog/] [wishbone_if.v] - Rev 24

Rev	Log message	Author	Age	Path
24	Use FIFO's for statistics clock domain crossing	antanguay	4192d 18h	/xge_mac/trunk/rtl/verilog/wishbone_if.v
23	Adding basic packet stats	antanguay	4193d 00h	/xge_mac/trunk/rtl/verilog/wishbone_if.v
20	Updates for Xilinx synthesis	antanguay	4484d 15h	/xge_mac/trunk/rtl/verilog/wishbone_if.v
12	Change interface to big endian, added serdes examples to testbench	antanguay	5270d 22h	/xge_mac/trunk/rtl/verilog/wishbone_if.v
7	New directory structure.	root	5549d 08h	/xge_mac/trunk/rtl/verilog/wishbone_if.v
2	Initial revision	antanguay	5831d 19h	/xge_mac/trunk/rtl/verilog/wishbone_if.v