URL https://opencores.org/ocsvn/xge_mac/xge_mac/trunk

Subversion Repositories xge_mac

[/] [xge_mac/] [trunk/] [rtl/] [verilog/] [xge_mac.v] - Rev 24

Rev	Log message	Author	Age	Path
24	Use FIFO's for statistics clock domain crossing	antanguay	4192d 20h	/xge_mac/trunk/rtl/verilog/xge_mac.v
23	Adding basic packet stats	antanguay	4193d 02h	/xge_mac/trunk/rtl/verilog/xge_mac.v
20	Updates for Xilinx synthesis	antanguay	4484d 17h	/xge_mac/trunk/rtl/verilog/xge_mac.v
12	Change interface to big endian, added serdes examples to testbench	antanguay	5271d 01h	/xge_mac/trunk/rtl/verilog/xge_mac.v
7	New directory structure.	root	5549d 10h	/xge_mac/trunk/rtl/verilog/xge_mac.v
6	Updated spec. Added mod[2:0] signals. Timing improvements.	antanguay	5825d 18h	/xge_mac/trunk/rtl/verilog/xge_mac.v
2	Initial revision	antanguay	5831d 22h	/xge_mac/trunk/rtl/verilog/xge_mac.v